PAGE BUFFERS AND OPERATION METHODS THEREOF, AND MEMORY DEVICES AND MEMORY SYSTEMS

Abstract: examples of the present application relate to the field of semiconductors, and disclose a page buffer and an operation method thereof, a memory device and a memory system. the page buffer includes latch circuits, wherein the latch circuits includes: a latch control configuration circuit connected with a first data node and a second data node, and configure the first data node and the second data node to different logic levels respectively in response to a configuration signal, wherein a logic level of the first data node is opposite to a logic level of the second data node; and a latch transmission circuit connected with the first data node, the second data node, and a sense node, and configured to: couple the second data node with the sense node in response to a transmission signal, to transmit a configuration result of the latch control configuration circuit to the sense node.

Inventor(s): Weiwei He

CPC Classification: G11C16/24 (Bit-line control circuits)

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