PAGE BUFFERS AND OPERATION METHODS THEREOF, MEMORY DEVICES, AND MEMORY SYSTEMS

Abstract: examples of the present application disclose a page buffer including a plurality of latch circuits. each latch circuit includes a resetting control circuit, a setting control circuit, a data transmission circuit, and a latch transmission circuit. the resetting control circuit is coupled to a first data node and configured to receive a first supply voltage, so as to determine a potential of the first data node. the setting control circuit is coupled to a second data node and configured to receive the first supply voltage, so as to determine a potential of the second data node. the data transmission circuit is coupled to the first data node and the second data node and configured to receive a second supply voltage. the latch transmission circuit is coupled to the first data node, the second data node, and a sense node. the first supply voltage is higher than the second supply voltage.

Inventor(s): Weiwei He, Ke Liang, Wei Huang

CPC Classification: G11C7/1087 (Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers)

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