NETWORK CREDIT RETURN MECHANISMS

Abstract: implementations of the present disclosure are directed to systems and methods for reducing design complexity and critical path timing challenges of credit return logic. a wide bus supports simultaneous transmission of multiple flits, one per lane of the wide bus. a source device transmitting flits on a wide bus selects from among multiple credit return options to ensure that only one of the multiple flits being simultaneously transmitted includes a credit return value. in some example embodiments, the receiving device checks only the flit of one lane of the wide bus (e.g., lane 0) for credit return data. in other example embodiments, the receiving device uses a bitwise-or to combine the credit return data of all received flits in a single cycle.

Inventor(s): Tony Brewer

CPC Classification: G06F13/364 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models ))

Search for rejections for patent application number 20250173292