SYSTEM-ON-CHIP AND POWER MANAGEMENT METHOD FOR SUCH A SYSTEM-ON-CHIP

Abstract: a system-on-chip includes a central processing unit, memories comprising a data memory and directly coupled to the central processing unit, where the memories store a first sequence of micro-instructions and a second sequence of micro-instructions to be executed in the central processing unit. the soc includes a power supply controller configured to set the central processing unit and the memories in a normal operation power supply mode in which the central processing unit and the memories are powered by a normal operation supply voltage, or in a standby power supply mode in which the central processing unit is no longer powered and the memories are powered by a standby supply voltage lower than the normal operation supply voltage and sufficient to preserve data stored in the memories. the central processing unit is configured to execute the first sequence of micro-instructions before being set in a standby power supply mode, and execute the second sequence of micro-instructions when leaving the standby power supply mode.

Inventor(s): Anne Joguet, Sidiki Sylla

CPC Classification: G06F1/3296 (Means for saving power)

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