MEMORY DEVICE USING SEMICONDUCTOR ELEMENT

Abstract: provided is a memory semiconductor device in which a p-type semiconductor region is formed at an n+layer to which a bit line is connected, an n-type semiconductor layer to which a source line is connected is further formed, a first gate insulating layer and a first gate conductor layer to which a word line is connected exist, a second gate insulating layer and a second gate conductor layer to which a plate line is connected are provided, and a distance from the n+layer to the first gate conductor layer is smaller than a distance up to the second gate conductor layer. at the time of an erase operation, the plate line and the source line have a positive electric potential of the same polarity or have a voltage of 0 v.

Inventor(s): Masakazu KAKUMU, Iwao KUNISHIMA, Koji SAKUI, Nozomu HARADA

CPC Classification: H10B12/20 (ELECTRONIC MEMORY DEVICES)

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