DIGITAL PHASE-LOCKED LOOPS

Abstract: a digital phase-locked loop includes a first clock divider, a decimation filter, a proportional integral filter, a signal conditioner, and a digitally controlled oscillator. the first clock divider divides a first clock signal including a first clock rate to generate a second clock signal including a second clock rate less than the first clock rate. the decimation filter converts an input signal at the first clock rate to an output signal at the second clock rate. the proportional integral filter filters the output signal at the second clock rate to generate a filtered output signal. the signal conditioner conditions the filtered output signal at the second clock rate to generate a conditioned output signal. the digitally controlled oscillator generates a carrier clock signal in response to the conditioned output signal.

Inventor(s): Saleh KARMAN

CPC Classification: H04L7/033 (using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop)

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