INTEGRATED CIRCUIT DEVICE

Abstract: provided is an integrated circuit device including first and second power lines each overlapping a first cell region, an inter-cell separation region, and a second cell region on a substrate in a vertical direction to the substrate, a first power tap cell penetrating through the substrate and receiving a first voltage from the first power line, a second power tap cell penetrating through the substrate and receiving, from the second power line, a second voltage different from the first voltage, and a dummy gate insulating bridge including first and second dummy gate insulating lines, which are apart from each other with the first and second power tap cells therebetween, and defining a vacuum space, and connected to the first and second dummy gate insulating lines.

Inventor(s): Jeewoong KIM, Jinkyu KIM, Yunsuk NAM, Yoonbeom PARK, Keunhwi CHO

CPC Classification: H01L23/5283 ({Geometry or} layout of the interconnection structure {( takes precedence; algorithms )})

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