BEOL INTEGRATION SOLUTION BASED ON DIRECT CMP TO IMPROVE INTERMETAL DIELECTRIC LAYER

Abstract: a process that helps ensure uniform height of conductive structures formed among intermetal dielectric layers of a wafer. when a metal layer is deposited on a first intermetal dielectric layer, a sealing layer is formed on the metal layer either before or after the metal layer is patterned to form metal interconnect structures. a first interlevel dielectric sub-layer is then formed on the sealing layer. a chemical mechanical planarization (cmp) process is then performed on the first interlevel dielectric sub-layer using the sealing layer as an etch stop. a second interlevel dielectric sub-layer is then formed on the first interlevel dielectric sub-layer.

Inventor(s): Fabrizio Fausto Renzo TOIA, Daniele CAPELLI, Samuele SCIARRILLO

CPC Classification: H01L21/76819 ({Smoothing of the dielectric (planarisation of insulating materials per se )})

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