READ OFFSET COMPENSATOR FOR ADJUSTING REFERENCE RESISTANCE USING COARSE OFFSET REFERENCE RESISTANCE AND FINE OFFSET REFERENCE RESISTANCE, AND MEMORY DEVICE INCLUDING THE SAME

Abstract: disclosed is a method and a memory device implementing the method. the method may include searching for a number of fail bits of output data output from a memory cell array of the memory device; determining a coarse offset reference resistance; searching for a number of fail bits of a first output data within a first reference resistance range based on the coarse offset reference resistance, determining a first fine offset reference resistance; searching for a number of fail bits of the second output data within a second reference resistance range based on the coarse offset reference resistance, determining a second fine offset reference resistance; and adjusting a reference resistance for a read operation using the coarse offset reference resistance and fine offset reference resistances, the fine offset reference resistances comprising resistances from the first fine offset reference resistance to the second fine offset reference resistance.

Inventor(s): Gyuseong KANG, Dohui KIM

CPC Classification: G11C11/1673 ({Reading or sensing circuits or methods})

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