SEMICONDUCTOR DEVICE

Abstract: disclosed is a memory device including a data pad, at least one merge node, a first data path coupled between the data pad and the at least one merge node and outputting, in a first mode, a first data signal to the at least one merge node based on a data signal, a reference signal and a mode selection signal; a second data path coupled between the data pad and the at least one merge node and outputting, in a second mode, a second data signal to the at least one merge node based on the data signal, the reference signal and the mode selection signal; and a synchronization path coupled to the at least one merge node and outputting, in one of the first and second modes, a corresponding signal of the first and second data signals as a data signal synchronized with at least one data strobe signal.

Inventor(s): Jae Hyeong HONG, Bon Kwang KOO, Ki Chang GWON, Chan Keun KWON, Beom Kyu SEO, Keun Seon AHN, Soon Sung AN, Sung Hwa OK, Ji Young LEE, Jun Seo JANG, Jae Hoon JUNG, Eun Ji CHOI

CPC Classification: G11C7/222 (Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management )

Search for rejections for patent application number 20250166679