APPARATUSES AND METHODS OF MEMORY ACCESS CONTROL

Abstract: apparatuses and methods for controlling access to memory cell matrices are described. an example apparatus includes: a plurality of memory cell matrices including memory cells, a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices; a section predecoder that activates one section signal among a plurality of corresponding section signals responsive to a portion of row address signals; a section selection control circuit that provides a set of first section sub signals including an active first section sub signal and a set of second section sub signals including an active second section sub signal based on the plurality of section signals; and a plurality of section selection circuits corresponding to the plurality of sections. one section selection circuit among the plurality of section selection circuits activates the corresponding section responsive to the active first and second section sub signals.

Inventor(s): Manami SENOO, Hidekazu NOGUCHI, Yoshio MIZUKANE

CPC Classification: G11C7/1039 ({using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers})

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