AUTOMATIC DETECTION OF MASK DEFECTS IN SEMICONDUCTOR PROCESSING

Abstract: detecting mask defects during semiconductor processing includes scanning, by one or more processors, a wafer during a lithography process of semiconductor processing. a first chip of a plurality of chips on the wafer is compared with a neighboring chip. in response to detecting a defect on the first chip during the comparison, a location of the defect on the first chip is stored by the one or more processors. the one or more processors select a second chip of the plurality of chips closest to a center of the wafer and scan the second chip storing inspection data corresponding to the second chip. the inspection data from the second chip is then compared with mask pattern data, and in response to the inspection data from the second chip matching the mask pattern data, the one or more processors allow the lithography process to continue.

Inventor(s): Choong Ho Lee, Donguk Choi

CPC Classification: G06T7/0006 ({using a design-rule based approach})

Search for rejections for patent application number 20250166159