HIGH BANDWIDTH CORE TO NETWORK-ON-CHIP INTERFACE

Abstract: an apparatus includes a first port set that includes an input port and an output port. the apparatus further includes a plurality of second port sets. each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. the plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

Inventor(s): Himanshu KAUL, Mark A. ANDERS, Gregory K. CHEN

CPC Classification: G06F13/4022 (ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models ))

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