MEMORY SYSTEMS AND CONTROLLERS FOR GENERATING A COMMAND ADDRESS AND METHODS OF OPERATING SAME

Abstract: a memory controller generates a command address signal (cas), and includes a first bit signal generator (bsg) configured to generate a data signal (ds) as a plurality of data bits, a second bsg configured to generate a command address bus inversion bit (cabib) having a logic level that is a function of a number of data bits within the ds having a predetermined logic level, and a parity bit generator configured to set a parity signal to a first logic level when a total number of data bits within the ds and the cabib having a high level is an even number. the cabib is set to a high logic level when “n”, which is a number of bits included in the cas, is a positive integer greater than one, and a number of data bits within the ds having a low level is greater than or equal to (n/2)−1.

Inventor(s): Sungrae Kim, Sungyong Cho, Minho Maeing, Gilyoung Kang, Hyeran Kim, Chisung Oh

CPC Classification: G06F12/06 (Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication ( takes precedence))

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