PROCESSING INSTRUCTIONS AT A PROCESSING UNIT CONFIGURED TO PERFORM PARALLEL PROCESSING

Abstract: a method of processing instructions at a processing unit having a parallel processing engine. during a mission cycle, a first set of mission operand values is processed in accordance with a mission instruction at a first processing instance to generate a first mission output. in parallel, a second set of mission operand values is processed in accordance with the mission instruction at a second processing instance to generate a second mission output. during a test cycle, a first set of test operand values is processed in accordance with a test instruction at the first processing instance to generate a first test output, and in parallel, a second set of test operand values is processed in accordance with the test instruction at the second processing instance to generate a second test output, where the first set of test operand values is the same as the second set of test operand values. the first test output and the second test output are compared and a fault signal is raised if the compared test outputs do not match.

Inventor(s): Daniel Wilkinson, Ian King

CPC Classification: G06F11/277 (with comparison between actual response and known fault-free response)

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