SELF-CONTAINED AND CONFIGURABLE DEBUGGING MECHANISM FOR STREAM-BASED HARDWARE ACCELERATORS

Abstract: a hardware accelerator includes a plurality of functional circuits, a stream switch, a plurality of direct memory access (dma) channels coupled to the plurality of functional circuits via the stream switch to stream data to and from functional circuits of the plurality of functional circuits, and a debug and trace unit coupled to the stream switch, wherein in operation, the debug and trace unit monitors a set of data signals to and from the stream switch via wired probes and implements one or more event counters, one or more triggers, and one or more tracers using components internal to the hardware accelerator including one or more registers of the hardware accelerator, and wherein the one or more tracers output trace data packets via the stream switch.

Inventor(s): Antonio DE VITA, David SIORPAES, Thomas BOESCH, Giuseppe DESOLI

CPC Classification: G06F11/221 (Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing)

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