PROCESSING UNIT CONFIGURED TO PERFORM PARALLEL PROCESSING

Abstract: a processing unit configured to perform parallel processing includes a parallel processing engine, the parallel processing engine including a plurality of processing instances configured to process instructions in parallel. test instruction insertion logic identifies an idle cycle of the parallel processing engine and inserts a test instruction for processing during the idle cycle by each of the plurality of processing instances so as to generate a respective plurality of test outputs. check logic compares a test output generated during the idle cycle by a first processing instance of the plurality of processing instances with a test output generated during the idle cycle by a second processing instance of the plurality of processing instances, and raises a fault signal if the compared test outputs do not match.

Inventor(s): Daniel Wilkinson, Ian King

CPC Classification: G06F9/3869 ({Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking})

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