SEPARATE BRANCH TARGET BUFFERS FOR DIFFERENT LEVELS OF CALLS

Abstract: a computing device (e.g., a processor) having a plurality of branch target buffers. a first branch target buffer in the plurality of branch target buffers is used in execution of a set of instructions containing a call to a subroutine. in response to the call to the subroutine, a second branch target buffer is allocated from the plurality of branch target buffers for execution of instructions in the subroutine. the second branch target buffer is cleared before the execution of the instructions in the subroutine. the execution of the instructions in the subroutine is restricted to access the second branch target buffer and blocked from accessing branch target buffers other than the second branch target buffer.

Inventor(s): Steven Jeffrey Wallach

CPC Classification: G06F9/3806 ({using address prediction, e.g. return stack, branch history buffer})

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