SYSTEM ON CHIP FOR REDUCING WAKE-UP TIME, METHOD OF OPERATING SAME, AND COMPUTER SYSTEM INCLUDING SAME

Abstract: a system on chip (soc) includes an internal read-only memory (rom) configured to store a first boot loader; a first internal static random access memory (sram) configured to receive a second boot loader output from a booting device, store the second boot loader, and perform a booting sequence according to control of the first boot loader; a second internal sram configured to receive a third boot loader output from the booting device, store the third boot loader, and perform a wake-up sequence according to control of the first boot loader; and a dynamic random access memory (dram) controller configured to load an operating system (os) from the booting device into a dram according to control of the second boot loader.

Inventor(s): Hee Dong SHIN

CPC Classification: G06F1/3287 (by switching off individual functional units in the computer system)

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