20240036975. MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE simplified abstract (Rambus Inc.)

MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE

Organization Name

Rambus Inc.

Inventor(s)

Frederick A. Ware of Los Altos Hills CA (US)

Brent S. Haukness of Sunnyvale CA (US)

Lawrence Lai of San Jose CA (US)

MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240036975 titled 'MEMORY COMPONENT WITH ERROR-DETECT-CORRECT CODE INTERFACE

Simplified Explanation

The abstract of this patent application describes a memory component that generates and stores check bits for error detection and correction codes (EDC). The memory component operates in three modes:

1. In the first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask signal lines. 2. In the second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. 3. In the third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line.

By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

• The memory component internally generates and stores check bits for error detection and correction codes.
• Three modes of operation are defined: read transaction, unmasked write transaction, and masked write transaction.
• In the read transaction mode, the check bits are sent to the memory controller along with the data.
• In the unmasked write transaction mode, the check bits are sent to the memory component on the data mask signal lines.
• In the masked write transaction mode, at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line.
• The EDC code can detect and correct errors that occur between the memory component and the memory controller.

Potential applications of this technology:

• Computer memory systems
• Data storage devices
• Communication systems

Problems solved by this technology:

• Error detection and correction in memory systems
• Improving data integrity and reliability
• Reducing the impact of errors on system performance

Benefits of this technology:

• Enhanced data reliability
• Improved system performance
• Simplified error detection and correction process

Original Abstract Submitted

a memory component internally generates and stores the check bits of error detect and correct code (edc). in a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (dm) signal lines. in a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. in a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. by sending the check bits along with the data, the edc code can be used to detect and correct errors that occur between the memory component and the memory controller.