20240012048. IP CORE TESTING APPARATUS simplified abstract (Infineon Technologies AG)

IP CORE TESTING APPARATUS

Organization Name

Infineon Technologies AG

Inventor(s)

Rajendra Prasad Manchikalapati of Bristol (GB)

RajaNataraj Sivaraj of Bristol (GB)

IP CORE TESTING APPARATUS - A simplified explanation of the abstract

This abstract first appeared for US patent application 20240012048 titled 'IP CORE TESTING APPARATUS

Simplified Explanation

The abstract describes a regression suite apparatus for semiconductor IP, which includes a knowledge graph that indicates the dependency between different functional blocks. The apparatus also includes a selector to choose a subset of tests based on the level of dependency between functional blocks, and a running apparatus to execute the selected tests on an updated design.

• The regression suite apparatus is designed for semiconductor IP.
• It includes a knowledge graph that defines the dependency between functional blocks.
• The knowledge graph includes weights representing the degree of dependency.
• The apparatus has an input for indicating changes in functional blocks in an updated design.
• A selector is used to choose a subset of tests based on the level of dependency.
• The selector selects tests from different levels, including tests for input functional blocks and tests for blocks dependent on the input block.
• The selected subset of tests is executed on the updated design using the running apparatus.

Potential applications of this technology:

• Semiconductor IP development and testing.
• Regression testing for updated designs.
• Verification and validation of functional blocks in semiconductor IP.

Problems solved by this technology:

• Efficient selection of tests based on the dependency between functional blocks.
• Automation of regression testing for semiconductor IP.
• Identification of changes in functional blocks and their impact on dependent blocks.

Benefits of this technology:

• Improved efficiency and accuracy in regression testing.
• Reduction in testing time and effort.
• Early detection of issues and dependencies in functional blocks.
• Enhanced reliability and quality of semiconductor IP.

Original Abstract Submitted

a regression suite apparatus for semiconductor ip having a plurality of functional blocks provides a knowledge graph defining, for each pair of first and second functional blocks, an indication of whether the second functional block depends on the first functional block; in case of a dependency, the knowledge graph comprises a weight representing a degree of dependency of the second functional block on the first functional block; an input for indicating functional blocks changed in an updated design; a selector arranged to select a subset of the tests by selecting numbers of tests of each of a plurality of different levels, wherein a first level selects tests corresponding to an input functional block and a second level selects tests corresponding to the input functional block in combination with second level blocks dependent on the input functional block; and apparatus for running the selected subset of tests on the updated design.