19017952. HARDWARE COHERENCE SIGNALING PROTOCOL (TEXAS INSTRUMENTS INCORPORATED)
HARDWARE COHERENCE SIGNALING PROTOCOL
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Abhijeet Ashok Chachad of Plano TX US
David Matthew Thompson of Dallas TX US
Pete Michael Hippleheuser of Murphy TX US
HARDWARE COHERENCE SIGNALING PROTOCOL
This abstract first appeared for US patent application 19017952 titled 'HARDWARE COHERENCE SIGNALING PROTOCOL
Original Abstract Submitted
An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad of Plano TX US
- David Matthew Thompson of Dallas TX US
- Naveen Bhoria of Plano TX US
- Pete Michael Hippleheuser of Murphy TX US
- G06F12/0811
- G06F9/30
- G06F9/38
- G06F9/46
- G06F9/54
- G06F11/30
- G06F12/0808
- G06F12/0815
- G06F12/0817
- G06F12/0831
- G06F12/084
- G06F12/0895
- G06F12/128
- G06F13/16
- CPC G06F12/0811