19012953. LOGIC CELL STRUCTURES AND RELATED METHODS (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.)

LOGIC CELL STRUCTURES AND RELATED METHODS

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor(s)

KUMAR Lalgudi of FREMONT CA US

RANJITH Kumar of HSINCHU CITY TW

MOHAMMED RABIUL Islam of AUSTIN TX US

JIANYANG Xu of HSINCHU CITY TW

LOGIC CELL STRUCTURES AND RELATED METHODS

This abstract first appeared for US patent application 19012953 titled 'LOGIC CELL STRUCTURES AND RELATED METHODS

Original Abstract Submitted

A method of forming an integrated circuit structure is provided. The method includes: providing a logic cell structure including a first input node, a second input node, and a pulling network connected to a reference voltage and an output node, wherein the pulling network includes a plurality of transistor segments; determining a delay associated with at least one of the first input node and the second input node; and connecting the plurality of transistor segments to the first input node, the second input node and the output node based at least in part on the determined delay.