19009302. LOGIC CELL WITH SMALL CELL DELAY (MEDIATEK INC.)
LOGIC CELL WITH SMALL CELL DELAY
Organization Name
Inventor(s)
Kin-Hooi Dia of Hsinchu City TW
Ho-Chieh Hsieh of Hsinchu City TW
LOGIC CELL WITH SMALL CELL DELAY
This abstract first appeared for US patent application 19009302 titled 'LOGIC CELL WITH SMALL CELL DELAY
Original Abstract Submitted
A semiconductor structure is provided. A logic cell with a logic function includes P-type and N-type transistors in first and second active regions over a semiconductor substrate, first and a second isolation structures on opposite edges of the first and second active regions, first and third transistors in the first and second active regions and between the first isolation structure and the P-type transistors, second and fourth transistors in the first and second active region and between the second isolation structure and the P-type transistors. Each of the N-type transistors and a respective P-type transistor shares a first gate electrode along the first direction. The first and third transistors share a second gate electrode extending along the first direction. The second and fourth transistors share a third gate electrode extending along the first direction. The P-type transistors and the N-type transistors are configured to perform the logic function.