19002241. Wiring Layer And Manufacturing Method Therefor (SEMICONDUCTOR ENERGY LABORATORY CO., LTD.)
Wiring Layer And Manufacturing Method Therefor
Organization Name
SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Inventor(s)
Tomoaki Moriwaka of Isehara JP
Shinya Sasagawa of Chigasaki Kanagawa JP
Wiring Layer And Manufacturing Method Therefor
This abstract first appeared for US patent application 19002241 titled 'Wiring Layer And Manufacturing Method Therefor
Original Abstract Submitted
To provide a miniaturized semiconductor device with low power consumption. A method for manufacturing a wiring layer includes the following steps: forming a second insulator over a first insulator; forming a third insulator over the second insulator; forming an opening in the third insulator so that it reaches the second insulator; forming a first conductor over the third insulator and in the opening; forming a second conductor over the first conductor; and after forming the second conductor, performing polishing treatment to remove portions of the first and second conductors above a top surface of the third insulator. An end of the first conductor is at a level lower than or equal to the top level of the opening. The top surface of the second conductor is at a level lower than or equal to that of the end of the first conductor.