18999134. DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL (TEXAS INSTRUMENTS INCORPORATED)
DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Devanathan Varadarajan of Allen TX US
Jose Luis Flores of Richardson TX US
Rejitha Nair of Southlake TX US
David Matthew Thompson of Dallas TX US
DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL
This abstract first appeared for US patent application 18999134 titled 'DISTRIBUTED MECHANISM FOR FINE-GRAINED TEST POWER CONTROL
Original Abstract Submitted
An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.