18976474. MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM (TEXAS INSTRUMENTS INCORPORATED)
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Abhijeet Ashok Chachad of Plano TX US
Timothy Anderson of University Park TX US
David Matthew Thompson of Dallas TX US
MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
This abstract first appeared for US patent application 18976474 titled 'MEMORY PIPELINE CONTROL IN A HIERARCHICAL MEMORY SYSTEM
Original Abstract Submitted
In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.