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18973511. TOPOLOGICAL SIMULATION OF LAYOUT DESIGN (Micron Technology, Inc.)

From WikiPatents

TOPOLOGICAL SIMULATION OF LAYOUT DESIGN

Organization Name

Micron Technology, Inc.

Inventor(s)

Yorio Takada of Tokyo JP

TOPOLOGICAL SIMULATION OF LAYOUT DESIGN

This abstract first appeared for US patent application 18973511 titled 'TOPOLOGICAL SIMULATION OF LAYOUT DESIGN

Original Abstract Submitted

Apparatuses, computer implemented methods and non-transitory computer-readable media storing instructions to implement simulating topological features of layout designs are disclosed. An example method includes: receiving information about the layout design including topological parameters in a verification area; defining a width and a length in first and second direction directions of one or more windows; defining first and second step sizes independently from the width and the length in the first and second directions for the one or more windows, the first step size being a distance between adjacent central points of the one or more windows in the first direction and the second step size being a distance between adjacent central points of the one or more windows in the second direction; extracting information about the layout design in the one or more windows at each of a plurality of window locations; and storing the information in a database.

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