18825616. ULTRA-LOW POWER TIMING CIRCUIT WITH PLL LOCKING (Northeastern University)
ULTRA-LOW POWER TIMING CIRCUIT WITH PLL LOCKING
Organization Name
Inventor(s)
Aatmesh Shrivastava of Weston MA (US)
ULTRA-LOW POWER TIMING CIRCUIT WITH PLL LOCKING
This abstract first appeared for US patent application 18825616 titled 'ULTRA-LOW POWER TIMING CIRCUIT WITH PLL LOCKING
Original Abstract Submitted
Methods, systems, and computer program products are presented herein for circuit timing using ultra-low power (ULP) timing circuit systems. A ULP timing circuit system comprises a receiver circuit, phase lock loop (PLL) circuit, crystal oscillator (XO) circuit, temperature sensing and calibration circuit, and temperature compensation circuit. The receiver circuit is configured to receive a reference clock signal. The XO circuit is configured to produce an output clock signal. The PLL circuit is configured to produce a control signal based on the reference clock signal and output clock signal. The temperature compensation circuit is configured to produce a compensation signal based on an operating temperature. The temperature sensing and calibration circuit is configured to sense the operating temperature and to calibrate the XO circuit based on the operating temperature, control signal, and compensation signal to lock a frequency of the output clock signal to the reference clock signal.