18775981. SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES (Micron Technology, Inc.)
SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES
Organization Name
Inventor(s)
Sai Krishna Mylavarapu of Folsom CA US
Shivasankar Gunasekaran of Erie CO US
Ameen D. Akel of Rancho Cordova CA US
Lance P. Johnson of Saint Paul MN US
Amy Rae Griffin of Boise ID US
SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES
This abstract first appeared for US patent application 18775981 titled 'SPARING TECHNIQUES IN STACKED MEMORY ARCHITECTURES
Original Abstract Submitted
Methods, systems, and devices for sparing techniques in stacked memory architectures are described. A memory system may implement a stacked memory architecture that includes a set of array dies stacked along a direction and a logic die coupled with the set of array dies. Each array die may include one or more memory arrays accessible using one or more first interface blocks of the array die. To support sparing, the memory system may remap access from one or more first memory arrays of the set of array dies to one or more second memory arrays of the set of array dies. Logic circuitry of the logic die may be operable to perform the remapping in accordance with one or more levels of granularity, such as at a die level, channel level, pseudo-channel level, bank level, or a combination thereof.