18749111. Hybrid Node Chiplet Stacking Design simplified abstract (TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.)

Hybrid Node Chiplet Stacking Design

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

Jen-Yuan Chang of Hsinchu City (TW)

Jheng-Hong Jiang of Hsinchu (TW)

Chin-Chou Liu of Hsinchu County (TW)

Long Song Lin of Taipei City (TW)

Hybrid Node Chiplet Stacking Design - A simplified explanation of the abstract

This abstract first appeared for US patent application 18749111 titled 'Hybrid Node Chiplet Stacking Design

The present disclosure involves methods for creating multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques like machine learning. These methods enable heterogenous integration, enhance design for manufacturability, and potentially reduce manufacturing costs and system size.

• Receiving a single chip design for a single process node chip
• Disassembling the single chip design into chiplets with different functions and process nodes
• Integrating the chiplets into a stacked chip package structure

Potential Applications: - Advanced packaging technologies - Semiconductor industry - Electronics manufacturing

Problems Solved: - Facilitates heterogenous integration - Enhances design for manufacturability - Reduces manufacturing costs and system size

Benefits: - Improved efficiency in design processes - Enhanced performance through integration of chiplets - Cost savings in manufacturing

Commercial Applications: Title: Advanced Packaging Solutions for Semiconductor Industry This technology can be utilized in various industries such as consumer electronics, automotive, and telecommunications for developing advanced and efficient packaging solutions.

Questions about Multichip, Hybrid Node Stacked Package Designs: 1. How does this technology impact the semiconductor industry?

  - This technology revolutionizes packaging designs, enabling more efficient and cost-effective solutions for semiconductor manufacturers.

2. What are the potential challenges in implementing multichip, hybrid node stacked package designs?

  - Some challenges may include compatibility issues between chiplets, optimizing integration processes, and ensuring reliability in the stacked package structure.

Original Abstract Submitted

The present disclosure is directed to methods for generating a multichip, hybrid node stacked package designs from single chip designs using artificial intelligence techniques, such as machine learning. The methods disclosed herein can facilitate heterogenous integration using advanced packaging technologies, enlarge design for manufacturability of single chip designs, and/or reduce cost to manufacture and/or size of systems provided by single chip designs. An exemplary method includes receiving a single chip design for a single chip of a single process node, wherein the single chip design has design specifications and generating a multichip, hybrid node design from the single chip design by disassembling the single chip design into chiplets having different functions and different process nodes based on the design specifications and integrating the chiplets into a stacked chip package structure.