METHOD AND SYSTEM FOR WAFER-LEVEL TESTING

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor(s)

JUN He of HSINCHU (TW)

YU-TING Lin of HSIN-CHU CITY (TW)

WEI-HSUN Lin of HSINCHU COUNTY (TW)

YUNG-LIANG Kuo of HSINCHU (TW)

YINLUNG Lu of HSINCHU (TW)

METHOD AND SYSTEM FOR WAFER-LEVEL TESTING - A simplified explanation of the abstract

This abstract first appeared for US patent application 18672047 titled 'METHOD AND SYSTEM FOR WAFER-LEVEL TESTING

The present disclosure introduces a method and system for testing semiconductor devices, involving energizing an integrated circuit (IC) on a wafer and applying a stress signal with specific sequences to the IC.

The method includes raising the voltage of the IC to a first level during a first period and applying a stress signal with first and second sequences during a subsequent period.
Each sequence of the stress signal consists of a ramp-up stage and a ramp-down stage, causing the voltage of the IC to fluctuate between second and third voltage levels.
The first sequence is longer in duration than the second sequence, providing a unique stress testing approach for semiconductor devices.

Potential Applications: - This technology can be used in the semiconductor industry for testing the reliability and performance of integrated circuits. - It can also be applied in research and development settings to assess the quality of semiconductor devices.

Problems Solved: - The method addresses the need for efficient and effective stress testing of semiconductor devices to ensure their functionality and durability.

Benefits: - Improved testing accuracy and reliability of semiconductor devices. - Enhanced quality control processes in semiconductor manufacturing. - Cost-effective solution for stress testing integrated circuits.

Commercial Applications: - This technology can be utilized by semiconductor manufacturers to enhance the quality assurance of their products. - It can also be integrated into testing equipment used in semiconductor fabrication facilities.

Questions about Semiconductor Device Testing: 1. How does the stress signal with specific sequences help in testing semiconductor devices?

  - The stress signal with ramp-up and ramp-down stages allows for comprehensive evaluation of the IC's performance under varying voltage levels.

2. What are the potential implications of using this method in semiconductor manufacturing processes?

  - The method can lead to improved product quality, reduced failure rates, and increased efficiency in semiconductor production.

Original Abstract Submitted

The present disclosure provides a method and a system for testing semiconductor device. The method includes the following operations: energizing an integrated circuit (IC) on a wafer by raising a voltage of the IC to a first voltage level during a first period, and applying to the IC a stress signal including a first sequence and a second sequence during a second period subsequent to the first period, each of the first sequence and the second sequence having a ramp-up stage and a ramp-down stage. The stress signal causes the voltage of the IC to fluctuate between a second voltage level and a third voltage level, wherein a duration of the first sequence is longer than that of the second sequence.