18665265. Complementary 2(N)-Bit Redundancy for Single Event Upset Prevention simplified abstract (Google LLC)
Complementary 2(N)-Bit Redundancy for Single Event Upset Prevention
Organization Name
Inventor(s)
Syed Shakir Iqbal of Bangalore (IN)
Complementary 2(N)-Bit Redundancy for Single Event Upset Prevention - A simplified explanation of the abstract
This abstract first appeared for US patent application 18665265 titled 'Complementary 2(N)-Bit Redundancy for Single Event Upset Prevention
The present disclosure discusses complementary 2(N)-bit redundancy for single event upset (SEU) prevention in integrated circuits.
- Integrated circuit includes data storage elements for storing data and complementary data values, as well as multi-bit data storage elements for both values.
- Voting logic enables a complementary data storage scheme with inter-circuit redundancy to prevent SEU.
- Voting logic allows for detection and correction of data value errors and dynamic programming based on SEU failures.
- The technology aims to enhance reliability and error correction capabilities in integrated circuits.
- By utilizing complementary data storage and dynamic voting logic, SEU prevention and error correction are improved.
Potential Applications: - Aerospace and defense industries for critical systems requiring high reliability. - Medical devices where data integrity is crucial for patient safety. - Telecommunications equipment to ensure uninterrupted communication services.
Problems Solved: - Mitigating single event upsets in integrated circuits. - Enhancing error detection and correction capabilities. - Improving overall reliability and performance of electronic systems.
Benefits: - Increased reliability and fault tolerance. - Enhanced data integrity and error correction. - Improved system performance and longevity.
Commercial Applications: Title: Enhanced Error Correction Technology for Critical Systems This technology can be applied in aerospace, medical, and telecommunications industries to ensure data integrity and system reliability.
Questions about Complementary 2(N)-bit Redundancy for SEU Prevention:
1. How does complementary data storage help prevent single event upsets in integrated circuits? Complementary data storage allows for error detection and correction by storing both data and complementary values, enhancing system reliability.
2. What are the potential applications of this technology beyond aerospace and defense industries? This technology can also be beneficial in medical devices and telecommunications equipment where data integrity is critical for operation.
Original Abstract Submitted
The present disclosure describes various aspects of complementary 2(N)-bit redundancy for single event upset (SEU) prevention. In some aspects, an integrated circuit includes a data storage element to store a data value, another data storage element to store a complementary data value, a multi-bit data storage element (e.g., a 2-bit storage element) to store both the data value and the complementary data value, and voting logic that may enable a complementary data storage scheme with inter-circuit redundancy to prevent SEU. Additionally, the voting logic of the integrated circuit may enable detection and correction of data value errors and/or enable programming of voting logic criteria, which may be implemented dynamically based on a type of SEU failures that are detected or corrected.
