HYBRID PARALLEL PROGRAMMING OF SINGLE-LEVEL CELL MEMORY

Organization Name

Inventor(s)

HYBRID PARALLEL PROGRAMMING OF SINGLE-LEVEL CELL MEMORY - A simplified explanation of the abstract

This abstract first appeared for US patent application 18649582 titled 'HYBRID PARALLEL PROGRAMMING OF SINGLE-LEVEL CELL MEMORY

The memory device described in the patent application includes a page buffer with multiple registers and a memory array configured as single-level cell (SLC) memory, with a set of sub-blocks coupled with the page buffer. Control logic is connected to the page buffer and is responsible for storing the first page of SLC data in the multiple registers, followed by storing a subsequent page of the SLC data in the same registers. The control logic then concurrently programs both the subsequent page and the first page of data stored in the registers to the set of sub-blocks, with some operations being performed in parallel.

The memory device features a page buffer with multiple registers.
The memory array is set up as single-level cell (SLC) memory.
A set of sub-blocks is connected to the page buffer.
Control logic manages the storage and programming of SLC data.
The control logic enables concurrent programming of multiple pages of data to the sub-blocks.

Potential Applications: - This technology can be used in solid-state drives (SSDs) for faster and more efficient data storage. - It can also be applied in embedded systems and mobile devices to enhance memory performance.

Problems Solved: - Improves the speed and efficiency of storing and programming data in memory devices. - Enhances the overall performance of memory arrays in various applications.

Benefits: - Faster data storage and retrieval processes. - Increased efficiency in programming data to memory arrays. - Enhanced performance and reliability of memory devices.

Commercial Applications: Title: Enhanced Memory Device for Improved Data Storage This technology can be utilized in the development of high-speed SSDs for consumer electronics, data centers, and industrial applications. The improved efficiency and performance of memory arrays can lead to faster data processing and enhanced user experience.

Questions about Memory Device Technology: 1. How does the control logic manage the storage and programming of data in the memory device? 2. What are the potential applications of this technology in various industries?

Original Abstract Submitted

A memory device includes a page buffer with multiple registers and a memory array, configured as single-level cell (SLC) memory, including a set of sub-blocks coupled with the page buffer. Control logic is operatively coupled with the page buffer and causes a first page of SLC data to be stored in the multiple registers. The control logic causes a subsequent page of the SLC data to be stored in the multiple registers. The control logic causes the subsequent page and the first page of the SLC data stored in the multiple registers to be concurrently programmed to the set of sub-blocks. The control logic causes at least some of the operations for programming the first page and the subsequent page to the set of sub-blocks to be performed in parallel.