READING A MULTI-LEVEL MEMORY CELL

Organization Name

Micron Technology, Inc.

Inventor(s)

Mattia Robustelli of Milano (IT)

Fabio Pellizzer of Boise ID (US)

Innocenzo Tortorelli of Cernusco Sul Naviglio (IT)

Agostino Pirovano of Milano (IT)

READING A MULTI-LEVEL MEMORY CELL - A simplified explanation of the abstract

This abstract first appeared for US patent application 18643126 titled 'READING A MULTI-LEVEL MEMORY CELL

Simplified Explanation: The patent application describes methods, systems, and devices for reading a multi-level memory cell that can store three or more logic states. The memory device applies different read voltages to determine the logic state stored in the cell and detects snapback events to accurately read the data.

The memory cell can store multiple logic states.
Different read voltages are applied to determine the logic state stored in the memory cell.
Snapback events are detected to ensure accurate reading of the data.
The logic state is determined based on the occurrence of snapback events.

Potential Applications: 1. Data storage devices 2. Computer memory systems 3. Embedded systems 4. Internet of Things (IoT) devices

Problems Solved: 1. Efficient reading of multi-level memory cells 2. Accurate determination of logic states 3. Enhanced data storage capabilities

Benefits: 1. Improved data storage efficiency 2. Enhanced memory reading accuracy 3. Increased storage capacity

Commercial Applications: The technology can be utilized in various data storage devices, computer memory systems, and IoT devices to enhance data storage efficiency and accuracy, catering to a wide range of commercial applications in the tech industry.

Questions about Multi-Level Memory Cell Reading: 1. How does the application of different read voltages help in determining the logic state stored in the memory cell? 2. What are the benefits of detecting snapback events in reading multi-level memory cells?

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Original Abstract Submitted

Methods, systems, and devices for reading a multi-level memory cell are described. The memory cell may be configured to store three or more logic states. The memory device may apply a first read voltage to a memory cell to determine a logic state stored by the memory cell. The memory device may determine whether a first snapback event occurred and apply a second read voltage based on determining that the first snapback event failed to occur based on applying the first read voltage. The memory device may determine whether a second snapback event occurred and determine the logic state based on whether the first snapback event or the second snapback event occurred.