MEMORY DEVICE AND METHOD

Organization Name

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor(s)

MEMORY DEVICE AND METHOD - A simplified explanation of the abstract

This abstract first appeared for US patent application 18615866 titled 'MEMORY DEVICE AND METHOD

The abstract describes an Input/Output (I/O) circuit for a memory device, which includes a charge integration circuit, a comparator, and a time-to-digital converter.

Charge integration circuit is connected to a bitline of the memory device and provides a sensing voltage based on a decrease in voltage on the bitline.
Comparator compares the sensing voltage with a reference voltage and generates an output voltage based on the comparison.
Time-to-digital converter converts the time associated with the output voltage to a digital value.

Potential Applications: - This technology can be used in various memory devices to improve data sensing and processing capabilities. - It can enhance the performance and efficiency of memory systems in applications such as computers, smartphones, and IoT devices.

Problems Solved: - The I/O circuit addresses the need for accurate sensing and conversion of analog signals in memory devices. - It helps in reducing errors and improving the overall reliability of data storage and retrieval processes.

Benefits: - Improved accuracy and efficiency in data sensing and processing. - Enhanced performance and reliability of memory devices. - Potential for faster data transfer speeds and reduced power consumption.

Commercial Applications: - The technology can be applied in the development of high-speed memory devices for consumer electronics, data centers, and other computing applications. - It has the potential to drive innovation in the memory industry and improve the overall user experience with electronic devices.

Questions about the technology: 1. How does the charge integration circuit improve the sensing capabilities of the memory device? 2. What are the key advantages of using a time-to-digital converter in the I/O circuit design?

Original Abstract Submitted

An Input/Output (I/O) circuit for a memory device is provided. The I/O circuit includes a charge integration circuit coupled to a bitline of the memory device. The charge integration circuit provides a sensing voltage based on a decrease of a voltage on the bitline. A comparator is coupled to the charge integration circuit. The comparator compares the sensing voltage with a reference voltage and provides an output voltage based on the comparison. A time-to-digital converter coupled to the comparator. The time to digital convertor converts a time associated with the output voltage to a digital value.