18503656. Hybrid Address Translation Cache Using DRAM (Western Digital Technologies, Inc.)
Hybrid Address Translation Cache Using DRAM
Organization Name
Western Digital Technologies, Inc.
Inventor(s)
Alexander Bazarsky of Holon IL
Hybrid Address Translation Cache Using DRAM
This abstract first appeared for US patent application 18503656 titled 'Hybrid Address Translation Cache Using DRAM
Original Abstract Submitted
Splitting an address translation cache (ATC) into two portions can reduce costs and maintain efficient retrieval of data. One portion can be disposed in a first location while a second portion can be disposed in a second location distinct from the first location. The first location can be in the controller. The second location can be in a host memory buffer (HMB) or in a memory device separate from the controller. To obtain translated addresses, untranslated addresses can be searched in the first portion and the corresponding translated addresses can be retrieved from the second portion. When invalidating untranslated addresses, the untranslated addresses of the first portion can be deleted without a need to delete corresponding translated addresses in the second portion. To improve ATC storage capacity, grouping of untranslated addresses is possible using most significant bytes (MSBs).