18492126. ADAPTIVE CLOCK GENERATION FOR SERIAL LINKS (NVIDIA Corporation)
ADAPTIVE CLOCK GENERATION FOR SERIAL LINKS
Organization Name
Inventor(s)
Brian Matthew Zimmer of Sunnyvale CA US
ADAPTIVE CLOCK GENERATION FOR SERIAL LINKS
This abstract first appeared for US patent application 18492126 titled 'ADAPTIVE CLOCK GENERATION FOR SERIAL LINKS
Original Abstract Submitted
Adaptive clock mechanisms for serial links utilizing a delay-chain-based edge generation circuit to generate a clock that is a faster (higher-frequency) version of an incoming digital clock. The base frequency of the link clock utilized by the line transmitters is determined by the (slower) clock utilized by the digital circuitry supplying data to the line transmitters. An edge generator that may be composed of only non-synchronous circuit elements multiplies the edges of the slower clock to generate the link clock and also a clock forwarded to the receiver at a phase offset from the link clock.