GATE FORMATION PROCESS

Organization Name

Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor(s)

Ming-Huei Lin of Hsinchu City TW

Kai-Yuan Cheng of Hsinchu County TW

Chih-Pin Tsao of Hsinchu County TW

Hsing-Kan Peng of Hsinchu County TW

Shih-Hsun Chang of Hsinchu TW

Shu-Hui Wang of Hsinchu City TW

Jeng-Ya Yeh of New Taipei City TW

GATE FORMATION PROCESS

This abstract first appeared for US patent application 18485602 titled 'GATE FORMATION PROCESS

Original Abstract Submitted

Methods for forming a gate structure of a multi-gate device are provided. An example method includes depositing a gate dielectric layer over first nanostructures over a first region of a substrate and second nanostructures over a second region of the substrate, depositing a first work function metal (WFM) layer over the first nanostructures and the second nanostructures, depositing a first hard mask (HM) layer over the first WFM layer, selectively removing the first HM layer and the first WFM layer over the first region, selectively removing the first HM layer over the second region, depositing a second WFM layer over the substrate, depositing a second HM layer over the second WFM layer, selectively removing the second HM layer and the second WFM layer over the first region, selectively removing the second HM layer over the second region, and depositing a third WFM layer over the substrate.