18478226. SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER (TEXAS INSTRUMENTS INCORPORATED)
SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Masamitsu Matsuura of BEPPU-SHI OITA-KEN JP
Daiki Komatsu of BEPPU-SHI OITA-KEN JP
Kengo Aoya of BEPPU-SHI OITA-KEN JP
SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER
This abstract first appeared for US patent application 18478226 titled 'SEMICONDUCTOR PACKAGE WITH AN INSULATION LAYER
Original Abstract Submitted
A semiconductor package includes a semiconductor wafer having a first connection pad and a second connection pad spaced apart by a semiconductor region of the semiconductor wafer. Portions of the semiconductor wafer are covered by a protective overcoat. The semiconductor package also includes a cap wafer mounted to the semiconductor wafer and overpassing the semiconductor region of the semiconductor wafer. The cap wafer extends between the first connection pad and the second connection pad of the semiconductor wafer. The semiconductor package further includes an insulation material overlaying the cap wafer. The insulation material comprising vias to the first connection pad and the second connection pad, the vias being filled with a conductive material.