18474511. TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS (STMicroelectronics International N.V.)
TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS
Organization Name
STMicroelectronics International N.V.
Inventor(s)
Akshay Kumar Jain of Bhopal IN
Jeena Mary George of Kattappana IN
TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS
This abstract first appeared for US patent application 18474511 titled 'TEST TIME REDUCTION IN CIRCUITS WITH REDUNDANCY FLIP-FLOPS
Original Abstract Submitted
According to an embodiment, a digital circuit with N number of redundant flip-flops is provided, each having a data input coupled to a common data signal. The digital circuit operates in a functional mode and a test mode. During test mode, a first flip-flop is arranged as part of a test path and N-1 flip-flops are arranged as shadow logic. A test pattern at the common data signal is provided and a test output signal is observed at an output terminal of the first flip-flop to determine faults within a test path of the first flip-flop. At the same cycle, the test output signals of each of the N-1 number of redundant flip-flops is observed through the functional path to determine faults.
