18448155. INTEGRATED CIRCUIT LAYOUT METHOD simplified abstract (Taiwan Semiconductor Manufacturing Co., Ltd.)
INTEGRATED CIRCUIT LAYOUT METHOD
Organization Name
Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor(s)
Wen-Shen Chou of Zhubei City (TW)
Yung-Chow Peng of Hsinchu (TW)
INTEGRATED CIRCUIT LAYOUT METHOD - A simplified explanation of the abstract
This abstract first appeared for US patent application 18448155 titled 'INTEGRATED CIRCUIT LAYOUT METHOD
Simplified Explanation
The abstract describes a method for generating an IC layout diagram, which involves positioning a resistor unit cell and a MOS unit cell in the diagram, overlapping them with via regions, and storing the diagram in a storage device.
- The method involves positioning a resistor unit cell and a MOS unit cell in an IC layout diagram.
- The resistor unit cell includes a resistor with a source/drain metal region.
- The resistor unit cell is overlapped with a first via region.
- The MOS unit cell is overlapped with a second via region.
- The first and second via regions are overlapped with a continuous conductive region.
- The resulting IC layout diagram is stored in a storage device.
Potential applications of this technology:
- Integrated circuit design and layout
- Semiconductor manufacturing
Problems solved by this technology:
- Efficient and accurate generation of IC layout diagrams
- Simplified placement and overlapping of different unit cells
Benefits of this technology:
- Improved productivity in IC design
- Enhanced accuracy in IC layout diagrams
- Streamlined manufacturing processes
Original Abstract Submitted
A method of generating an IC layout diagram includes positioning a resistor unit cell in the IC layout diagram, a resistor of the resistor unit cell including a source/drain metal region, positioning a MOS unit cell in the IC layout diagram, overlapping the resistor unit cell with a first via region, overlapping the MOS unit cell with a second via region, overlapping the first and second via regions with a continuous conductive region, and storing the IC layout diagram in a storage device.
