18447326. MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME simplified abstract (SK hynix Inc.)

MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

Organization Name

SK hynix Inc.

Inventor(s)

Jae Yong Son of Gyeonggi-do (KR)

Dae Sung Kim of Gyeonggi-do (KR)

Min Su Choi of Gyeonggi-do (KR)

MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447326 titled 'MEMORY CONTROLLER AND MEMORY SYSTEM INCLUDING THE SAME

The abstract describes a memory controller that performs error correction decoding on data read by read retry operations, using retry fail voltages and syndrome weights stored in a buffer memory to optimize read voltages.

• Error correction circuit performs error correction decoding on data read by read retry operations
• Buffer memory stores decoding history information including retry fail voltages and syndrome weights
• Processor determines an optimally estimated read voltage based on the relationship between changes in syndrome weights and retry fail voltages
• Data is read using the optimally estimated read voltage to the error correction circuit

Potential Applications: - Data storage systems - Computer memory systems - Error correction technologies

Problems Solved: - Improving data read accuracy - Enhancing memory system performance - Optimizing read voltages for error correction

Benefits: - Increased data reliability - Enhanced memory system efficiency - Improved error correction capabilities

Commercial Applications: Title: "Optimized Memory Controller for Enhanced Data Read Accuracy" This technology can be utilized in various industries such as data centers, telecommunications, and consumer electronics for improved data storage and retrieval processes.

Prior Art: Researchers can explore existing patents related to memory controllers, error correction circuits, and data storage technologies to understand the evolution of similar innovations in the field.

Frequently Updated Research: Stay updated on advancements in error correction algorithms, memory system architectures, and data storage technologies to enhance the performance of memory controllers in the future.

Questions about Memory Controller Optimization: 1. How does the buffer memory store decoding history information? The buffer memory stores retry fail voltages and syndrome weights for optimizing read voltages in the memory controller. 2. What is the threshold number of times for read retry operations to trigger the determination of an optimally estimated read voltage? The processor determines an optimally estimated read voltage when the number of times read retry operations fail reaches a specific threshold.

Original Abstract Submitted

Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.