18435323. PHASE-LOCKED LOOP REFERENCE CLOCK MANAGEMENT simplified abstract (TEXAS INSTRUMENTS INCORPORATED)
PHASE-LOCKED LOOP REFERENCE CLOCK MANAGEMENT
Organization Name
TEXAS INSTRUMENTS INCORPORATED
Inventor(s)
Abhijit Patki of Bangalore (IN)
PHASE-LOCKED LOOP REFERENCE CLOCK MANAGEMENT - A simplified explanation of the abstract
This abstract first appeared for US patent application 18435323 titled 'PHASE-LOCKED LOOP REFERENCE CLOCK MANAGEMENT
Simplified Explanation
The abstract describes a patent application for a device that includes a phase-locked loop (PLL) with a reference input, a storage element, and a reference clock generator with a programmable clock divider. The reference clock generator adjusts the divide ratio of the clock divider based on the value in the storage element to keep the frequency of the reference clock output constant when the frequency of the interface clock input changes.
- The device includes a phase-locked loop (PLL) with a reference input.
- It has a storage element and a reference clock generator with a programmable clock divider.
- The reference clock generator adjusts the divide ratio of the clock divider based on the value in the storage element.
- This adjustment ensures that the frequency of the reference clock output remains constant even when the frequency of the interface clock input changes.
Potential Applications
This technology could be applied in various electronic devices that require stable clock signals, such as communication systems, data processing units, and digital signal processing applications.
Problems Solved
1. Maintains a stable reference clock output frequency despite changes in the interface clock input frequency. 2. Provides accurate timing synchronization for different components within electronic devices.
Benefits
1. Improved reliability and performance of electronic devices. 2. Simplified clock signal management. 3. Enhanced overall system efficiency.
Potential Commercial Applications
"Stable Clock Signal Technology for Electronic Devices"
Possible Prior Art
There may be prior art related to clock signal synchronization techniques in electronic devices, but specific examples are not provided in the abstract.
Unanswered Questions
How does this technology compare to existing clock synchronization methods in terms of accuracy and efficiency?
This article does not provide a direct comparison with existing clock synchronization methods, leaving the reader to wonder about the advantages of this technology over current solutions.
What are the specific electronic devices or industries that could benefit the most from this technology?
The abstract mentions potential applications in various electronic devices, but it does not specify which industries or devices would see the most significant improvements from implementing this technology.
Original Abstract Submitted
A device includes a phase-locked loop (PLL) having a reference input. The device has a storage element and a reference clock generator having an interface clock input, a reference clock output, and a programmable clock divider. The reference clock generator is coupled to the storage element. The reference clock output is coupled to the reference input. The reference clock generator is configured to change a divide ratio for the programmable clock divider based on a value in the storage element such that a frequency of the reference clock output remains unchanged when a frequency of the interface clock input changes.
