18428603. SEMICONDUCTOR DEVICE AND METHODS OF FORMATION (Taiwan Semiconductor Manufacturing Company, Ltd.)
SEMICONDUCTOR DEVICE AND METHODS OF FORMATION
Organization Name
Taiwan Semiconductor Manufacturing Company, Ltd.
Inventor(s)
Huan-Chieh Su of Tianzhong Township TW
Chih-Hao Wang of Baoshan Township TW
SEMICONDUCTOR DEVICE AND METHODS OF FORMATION
This abstract first appeared for US patent application 18428603 titled 'SEMICONDUCTOR DEVICE AND METHODS OF FORMATION
Original Abstract Submitted
Techniques described herein include forming respective (different) types of metal silicide layers for p-type source/drain regions and n-type source/drain regions of nanostructure transistors of a semiconductor device in a selective manner that reduces process complexity. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) of a first nanostructure transistor, and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective) of a second nanostructure transistor. This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.