WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

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WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

This abstract first appeared for US patent application 18420135 titled 'WIRING SUBSTRATE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

Original Abstract Submitted

A wiring substrate may include a core portion, an upper peripheral portion on a top surface of the core portion, and a lower peripheral portion on a bottom surface of the core portion. The upper peripheral portion may include a bridge chip provided on the top surface of the core portion, upper insulating patterns provided on the top surface of the core portion to cover the bridge chip, and upper interconnection patterns in the upper insulating patterns. The lower peripheral portion may include a dummy structure on the bottom surface of the core portion, lower insulating patterns on the bottom surface of the core portion to cover the dummy structure, and lower interconnection patterns in the lower insulating patterns. A mean thermal expansion coefficient of the upper peripheral portion may be substantially equal to a mean thermal expansion coefficient of the lower peripheral portion.