18403930. 3-D DRAM WORDLINE PARTITION AND STAIRCASE CONTACTS (Applied Materials, Inc.)
3-D DRAM WORDLINE PARTITION AND STAIRCASE CONTACTS
Organization Name
Inventor(s)
Chang Seok Kang of Santa Clara CA US
Sony Varghese of Manchester MA US
Fredrick Fishburn of Belmont CA US
3-D DRAM WORDLINE PARTITION AND STAIRCASE CONTACTS
This abstract first appeared for US patent application 18403930 titled '3-D DRAM WORDLINE PARTITION AND STAIRCASE CONTACTS
Original Abstract Submitted
Memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density. In a 3D DRAM with stacked unit cell layers of one or more embodiments, it is necessary to reduce the area of a unit cell in order to increase bit density per unit area for a given number of stacked cells. In one or more embodiments, n wordlines (nWL, n is an integer≥2) share a contact pad. The shared nWLs are separated by n bitlines (BLs) to assign every cell independently one WL and one BL.