18382973. CHIP PACKAGE WITH TAMPER PREVENTION (Advanced Micro Devices, Inc.)
CHIP PACKAGE WITH TAMPER PREVENTION
Organization Name
Inventor(s)
Deepak Vasant Kulkarni of Austin TX US
Richard E. George of Santa Clara CA US
Terry Eugene Richardson of Austin TX US
CHIP PACKAGE WITH TAMPER PREVENTION
This abstract first appeared for US patent application 18382973 titled 'CHIP PACKAGE WITH TAMPER PREVENTION
Original Abstract Submitted
A chip package includes a package substrate and an integrated circuit (IC) die disposed on the package substrate. The IC dies includes a security asset. The chip package also includes a glass based shield selectively disposed on the IC die and above the security asset. The glass based shield is configured to block access to the security asset. In some embodiments, the chip package includes an oxide layer disposed between the glass based shield and the IC die. In some embodiments, the chip package includes a detection module and a wire connecting the detection module to the glass based shield. The detection module is configured to generate and send a serial bit stream to the glass based shield. The detection module is also configured to monitor for changes in the serial bit stream returning from the glass based shield. Changes detected in the serial bit stream indicates the glass based shield has been tampered.