18381557. PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PROCESSOR-BASED DEVICES (Ampere Computing LLC)
PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PROCESSOR-BASED DEVICES
Organization Name
Inventor(s)
Bret Leslie Toll of Hillsboro OR US
Benjamin Crawford Chaffin of Portland OR US
George Van Horn Leming, Iii of Lake Oswego OR US
Jonathan Christopher Perry of Portland OR US
PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PROCESSOR-BASED DEVICES
This abstract first appeared for US patent application 18381557 titled 'PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PROCESSOR-BASED DEVICES
Original Abstract Submitted
Performing instruction fetch pipeline synchronization (IFPS) in processor-based devices is disclosed herein. In some exemplary aspects, a processor-based device provides multiple processors including a remote processor. The remote processor receives, from an issuing processor, a translation lookaside buffer (TLB) invalidation (TLBI) request indicating a request to invalidate an address translation, and subsequently receives an IFPS request from the issuing processor. The remote processor determines that any previously received TLBI requests including the most recent TLBI request have completed. Upon receiving the IFPS request, the remote processor determines that all instructions within a fetch pipeline portion that were potentially fetched using address translations older than the IFPS request have proceeded from the fetch pipeline portion of an instruction processing circuit to an execution pipeline portion of the instruction processing circuit. The remote processor then performs a data synchronization barrier (DSB) operation, and issues a synchronization acknowledgement to the issuing processor.