18379928. INTERFACIAL LAYER SCALING PROCESSES FOR SEMICONDUCTOR DEVICES (Applied Materials, Inc.)
INTERFACIAL LAYER SCALING PROCESSES FOR SEMICONDUCTOR DEVICES
Organization Name
Inventor(s)
Srinivas Gandikota of Santa Clara CA US
Seshadri Ganguli of San Jose CA US
Geetika Bajaj of Cupertino CA US
Debaditya Chatterjee of Sunnyvale CA US
Hsin-Jung Yu of Santa Clara CA US
Tuerxun Ailihumaer of Santa Clara CA US
INTERFACIAL LAYER SCALING PROCESSES FOR SEMICONDUCTOR DEVICES
This abstract first appeared for US patent application 18379928 titled 'INTERFACIAL LAYER SCALING PROCESSES FOR SEMICONDUCTOR DEVICES
Original Abstract Submitted
Methods of scaling the thickness of the interfacial layer in electronic devices, such as NMOS transistors and PMOS transistors are described. Some embodiments provide a metal film or a metal nitride film that reduces the thickness of the interfacial layer by scavenging unbound oxygen from the interfacial layer (e.g., silicon oxide (SiOx)) and the high-κ dielectric layer (e.g., hafnium oxide (HfOx)). Some embodiments advantageously include annealing the semiconductor substrate to promote or accelerate the scavenging.
- Applied Materials, Inc.
- Srinivas Gandikota of Santa Clara CA US
- Yixiong Yang of Fremont CA US
- Seshadri Ganguli of San Jose CA US
- Geetika Bajaj of Cupertino CA US
- Debaditya Chatterjee of Sunnyvale CA US
- Hsin-Jung Yu of Santa Clara CA US
- Tuerxun Ailihumaer of Santa Clara CA US
- Tengzhou Ma of San Jose CA US
- Lin Sun of Milpitas CA US
- H01L29/40
- H01L21/324
- H01L29/49
- H01L29/51
- CPC H10D64/01
